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FEATURES 2-Channel, 24-Bit - ADC Pin Configurable (No Programmable Registers) Pin Selectable Input Channels Pin Programmable Input Ranges ( 2.56 V or 160 mV) Fixed 19.79 Hz Update Rate Simultaneous 50 Hz and 60 Hz Rejection 24-Bit No Missing Codes 18.5-Bit p-p Resolution ( 2.56 V Range) 16.5-Bit p-p Resolution ( 160 mV Range) INTERFACE Master or Slave Mode of Operation Slave Mode 3-Wire Serial SPITM, QSPITM, MICROWIRETM, and DSP-Compatible Schmitt Trigger on SCLK POWER Specified for Single 3 V and 5 V Operation Normal: 1.3 mA @ 3 V Power-Down: 9 A ON-CHIP FUNCTIONS Rail-Rail Input Buffer and PGA APPLICATIONS Sensor Measurement Industrial Process Control Temperature Measurement Pressure Measurements Weigh Scales Portable Instrumentation
Read Only, Pin Configured 24-Bit - ADC AD7782
FUNCTIONAL BLOCK DIAGRAM
VDD GND REFIN(+) REFIN(-) XTAL1 XTAL2
AD7782
OSCILLATOR AND PLL
AIN1(+) AIN1(-) AIN2(+) AIN2(-) MUX BUF PGA 24-BIT ADC
SERIAL INTERFACE AND CONTROL LOGIC
DOUT/RDY SCLK MODE
CS
CH1/CH2
RANGE
BASIC CONNECTION DIAGRAM
POWER SUPPLY VDD
AD7782
ANALOG INPUT ANALOG INPUT REFERENCE INPUT AIN1(+) AIN1(-) AIN2(+) AIN2(-) REFIN(+) REFIN(-) GND CS DOUT/RDY SCLK XTAL1 XTAL2 32.768kHz CRYSTAL DIGITAL INTERFACE
GENERAL DESCRIPTION
The AD7782 is a complete analog front end for low-frequency measurement applications. The 24-bit sigma-delta ADC contains two fully differential analog input channels that can be configured with a gain of 1 or 16 allowing full-scale input signal ranges of 2.56 V or 160 mV from a +2.5 V differential reference input. The AD7782 has an extremely simple, read-only digital interface which can be operated in master mode or slave mode. There are no on-chip registers to be programmed. The input signal range and input channel selection are configured using two external pins.
The device operates from a 32.768 kHz crystal with an on-chip PLL generating the required internal operating frequency. The output data rate from the part is fixed via the master clock at 19.79 Hz and provides simultaneous 50 Hz and 60 Hz rejection at this update rate. Eighteen-bit p-p resolution can be obtained at this update rate. The part operates from a single 3 V or 5 V supply. When operating from 3 V supplies, the power dissipation for the part is 3.9 mW. The AD7782 is available in a 16-lead TSSOP package. Another part in the AD778x family is the AD7783. It is similar to the AD7782 except it has two integrated current sources and only one differential input channel.
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD7782-SPECIFICATIONS XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T
Parameter
ADC CHANNEL SPECIFICATION Output Update Rate ADC CHANNEL No Missing Codes2 Resolution Output Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error Gain Drift vs. Temperature Power Supply Rejection (PSR) ANALOG INPUTS Differential Input Voltage Ranges ADC Range Matching Absolute AIN Voltage Limits Analog Input Current2 DC Input Current DC Input Current Drift Normal-Mode Rejection2, 3 @ 50 Hz @ 60 Hz Common-Mode Rejection @ DC @ 50 Hz2 @ 60 Hz2 REFERENCE INPUT REFIN Voltage REFIN Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal-Mode Rejection2, 3 @ 50 Hz @ 60 Hz Common-Mode Rejection @ DC @ 50 Hz @ 60 Hz LOGIC INPUTS All Inputs Except SCLK and XTAL12 VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt-Triggered Input)2 VT(+) VT(-) VT(+) - VT(-) VT(+) VT(-) VT(+) - VT(-)
(VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(-) = GND; GND = 0 V; MIN to TMAX unless otherwise noted.)
Unit
Hz nom Bits min Bits p-p Bits p-p ppm of FSR max V typ nV/C typ V typ ppm/C typ dB typ dB typ mV nom V nom V typ V min V max nA max pA /C typ dB min dB min dB min dB min dB min V nom V min V max V min V max A/V typ nA/V/C typ dB min dB min dB typ dB typ dB typ 50 Hz 1 Hz 60 Hz 1 Hz Input Range = 160 mV, VIN = 1/16 V 125 dB typ, 110 dB typ when Input Range = 2.56 V 50 Hz 1 Hz 60 Hz 1 Hz REFIN = REFIN(+) - REFIN(-)
AD7782B
19.79 24 16 18 See Table I 10 3 10 10 0.5 100 85 160 2.56 2 GND + 100 mV VDD - 100 mV 1 5 60 94 105 100 100 2.5 1 VDD GND - 30 mV VDD + 30 mV 0.5 0.01 60 94 100 110 110
Test Conditions
160 mV Range, RANGE = 0 2.56 V Range, RANGE = 1 Typically 2 ppm FSR =
2 x 1.024 REFIN Gain
AIN(+) = AIN(-) = 2.5 V VDD = 3 V Input Range = 160 mV, VIN = 1/16 V Input Range = 2.56 V, VIN = 1 V RANGE = 0 RANGE = 1 Input Voltage = 159 mV on Both Ranges
50 Hz 1 Hz 60 Hz 1 Hz Input Range = 160 mV, VIN = 1/16 V 50 Hz 1 Hz 60 Hz 1 Hz
0.8 0.4 2.0 1.4/2 0.8/1.4 0.3/0.85 0.95/2 0.4/1.1 0.3/0.85
V max V max V min V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max
VDD = 5 V VDD = 3 V VDD = 3 V or 5 V VDD = 5 V VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VDD = 3 V
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AD7782
Parameter
LOGIC INPUTS (continued) XTAL1 Only2 VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage Input Currents Input Capacitance LOGIC OUTPUTS (Excluding XTAL2) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding START-UP TIME From Power-On POWER REQUIREMENTS Power Supply Voltage VDD - GND Power Supply Currents IDD Current (Normal Mode)4 IDD (Power-Down Mode, CS = 1)
AD7782B
Unit
Test Conditions
0.8 3.5 0.4 2.5 1 -70 10 VDD - 0.6 0.4 4 0.4 10 10 Offset Binary 300
V max V min V max V min A max A max pF typ V min V max V min V max A max pF typ
VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = VDD VIN = GND, Typically -40 A at 5 V and -20 A at 3 V All Digital Inputs VDD = 3 V, ISOURCE = 100 A VDD = 3 V, ISINK = 100 A VDD = 5 V, ISOURCE = 200 A VDD = 5 V, ISINK = 1.6 mA
ms typ
2.7/3.6 4.75/5.25 1.5 1.7 9 24
V min/max V min/max mA max mA max A max A max
VDD = 3 V nom VDD = 5 V nom VDD = 3 V, 1.3 mA typ VDD = 5 V, 1.5 mA typ VDD = 3 V, 6 A typ VDD = 5 V, 20 A typ
NOTES 1 Temperature Range -40C to +85C. 2 Guaranteed by design and/or characterization data on production release. 3 When a 28.8 kHz crystal is used, normal mode rejection is improved so that the rejection equals 75 dB at 50 1 Hz and equals 66 dB at 60 1 Hz. 4 Normal Mode refers to the case where the ADC is running. Specifications subject to change without notice.
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AD7782 TIMING CHARACTERISTICS1, 2
Parameter t1 tADC t2 t3 t4 t5 3 t8 5 t9 t10 Slave Mode Timing t6 t7 Master Mode Timing t6 t7 t11 30.5176 50.54 0 0 60 80 2 x t ADC 0 60 80 10 80 0 10 80 100 100 t1/2 t1/2 t1/2 3t1/2
(VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = VDD unless otherwise noted.)
Unit s typ ms typ ns min ns min ns max ns max ns typ ns min ns max ns max ns min ns max ns min ns min ns max ns min ns min s typ s typ s min s max Conditions/Comments Crystal Oscillator Period 19.79 Hz Update Rate CH1/CH2 Select to CS Setup Time CS Falling Edge to DOUT Active VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V Channel Settling Time SCLK Active Edge to Data Valid Delay4 VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V Bus Relinquish Time after CS Inactive Edge CS Rising Edge to SCLK Inactive Edge Hold Time SCLK Inactive to DOUT High
Limit at TMIN, TMAX (B Version)
SCLK High Pulsewidth SCLK Low Pulsewidth SCLK High Pulsewidth SCLK Low Pulsewidth DOUT Low to First SCLK Active Edge4
NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 2. 3 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
ISINK (1.6mA WITH VDD = 5V 100 A WITH VDD = 3V)
TO OUTPUT PIN
1.6V 50pF
ISOURCE ( 200 A WITH VDD = 5V 100 A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization
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AD7782
CH1/CH2 (I)
t2
CS (I)
t3 t4
DOUT/RDY MSB LSB MSB LSB
t9
t8
t5
SLAVE MODE SCLK (I)
t10 t7 t6
t5 t11
MASTER MODE SCLK (O)
t7 t6
I = INPUT TO AD7782, O = OUTPUT FROM AD7782 SLAVE MODE IS SELECTED BY TYING THE MODE PIN LOW, WHILE MASTER MODE IS SELECTED BY TYING THE MODE PIN HIGH.
Figure 2. Slave/Master Mode Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . . -0.3 V to VDD + 0.3 V Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . 30 mA Digital Input Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .97.9C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7782BRU EVAL-AD7782EB
Temperature Range -40C to +85C
Package Description TSSOP Evaluation Board
Package Option RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7782 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7782
PIN CONFIGURATION
XTAL1 1 REFIN(+) 2 REFIN(-) 3 AIN1(+) 4
16 XTAL2 15 VDD 14 GND
13 MODE TOP VIEW AIN1(-) 5 (Not to Scale) 12 DOUT/RDY 11 CS 10 SCLK 9 RANGE
AD7782
AIN2(+) 6 AIN2(-) 7 CH1/CH2 8
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 XTAL1 REFIN(+)
Function
11
12
13 14 15 16
Input to the 32.768 kHz Crystal Oscillator Inverter. Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND +1 V. The nominal reference voltage (REFIN(+) - REFIN(-)) is 2.5 V, but the part functions with a reference from 1 V to VDD. REFIN(-) Negative Reference Input. This reference input can lie anywhere between GND and VDD - 1 V. AIN1(+) Analog Input. AIN1(+) is the positive terminal of the fully-differential analog input pair AIN1(+)/AIN1(-). AIN1(-) Analog Input. AIN1(-) is the negative terminal of the fully-differential analog input pair AIN1(+)/AIN1(-). AIN2(+) Analog Input. AIN2(+) is the positive terminal of the fully-differential analog input pair AIN2(+)/AIN2(-). AIN2(-) Analog Input. AIN2(-) is the negative terminal of the fully-differential analog input pair AIN2(+)/AIN2(-). CH1/CH2 Channel Select, Logic Input. With CH1/CH2 = 0, channel AIN1(+)/AIN1(-) is selected while the active channel is AIN2(+)/AIN2(-) when CH1/CH2 = 1. RANGE Logic Input which configures the input range on the internal PGA. With RANGE = 0, the full-scale input range is 160 mV while the full-scale input range equals 2.56 V when RANGE = 1 for a +2.5 V Reference. SCLK Serial Clock Input/Output for Data Transfers from the ADC. When the device is operated in master mode, SCLK is an output with one SCLK period equal to one XTAL period. In slave mode, SCLK is generated by an external source. In slave mode, all the data can be transmitted on a continuous train of pulses. Alternatively, SCLK can be a noncontinuous clock with the information being transmitted from the AD7782 in smaller batches of data. SCLK is Schmitt triggered (slave mode) making the interface suitable for optoisolated applications. CS Chip Select Input. CS is an active low logic input used to select the AD7782. When CS is low, the PLL establishes lock and allows the AD7782 to initiate a conversion on the selected channel. When CS is high, the conversion is aborted, DOUT and SCLK are three-stated, the AD7782 enters standby mode and any conversion result in the output shift register is lost. DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose in this interface. When a conversion is initiated, DOUT/RDY goes high and remains high until the conversion is complete. DOUT/RDY will then return low to indicate that valid data is available to be read from the device. In slave mode, this acts as an interrupt to the processor indicating that valid data is available. If data is not read after a conversion, DOUT/RDY will go high before the next update occurs. In master mode, DOUT/RDY goes low for at least half an SCLK cycle before the device produces SCLKs. When SCLK becomes active, data is output on the DOUT/RDY pin. Data is output on the falling SCLK edge and is valid on the rising edge. MODE The MODE pin selects master or slave mode of operation. When MODE = 0, the AD7782 operates in master mode while the AD7782 is configured for slave mode when MODE = 1. GND Ground Reference Point for the AD7782. VDD Supply Voltage, 3 V or 5 V Nominal. XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter.
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AD7782 Typical Performance Characteristics
9 8
2.5 2.56V RANGE 3.0
7
RMS NOISE - V
6 5 4 3 2
2.0 VDD = 5V VREF = 2.5V TA = 25 C 160mV RANGE
1.5
1.0
0.5
1
8388382 8388449 8388499 8388547 8388579 8388615 8388754 8388779 8388805 8388841 8388874 8388906 8388941 8388687 8388721 8388039 8388985 8389033 8388657 8389110
0
0 1.0
1.5
2.0
2.5
3.0 VREF - V
3.5
4.0
4.5
5.0
TPC 1. Noise Distribution Histogram
TPC 2. RMS Noise vs. Reference Input
ADC CIRCUIT INFORMATION Overview
The output rate of the AD7782 (fADC) equals:
f ADC = 32.768 x 10 3 / (69 x 8 x 3)
The AD7782 incorporates an analog multiplexer with a - ADC channel, on-chip programmable gain amplifier, and on-chip digital filtering intended for the measurement of wide dynamic range, low-frequency signals such as those in weigh-scale, strain-gage, pressure transducer, or temperature measurement applications. This ADC input is buffered and can be programmed to have an input voltage range of 160 mV or 2.56 V. The input channels are configured as two fully differential inputs. Buffering the input channels means that the part can accommodate significant source impedances on the analog inputs and that R, C filtering (for noise rejection or RFI reduction) can be placed on the analog inputs if required. The device requires an external reference of +2.5 V nominal. Figure 3 shows the basic connections required to operate the part.
POWER SUPPLY 10 F 0.1 F
while the settling time equals:
2 t SETTLE = = 2 x t ADC f ADC
Normal-mode rejection is the major function of the digital filter on the AD7782. Simultaneous 50 Hz and 60 Hz rejection of better than 60 dB is achieved as notches are placed at both 50 Hz and 60 Hz. Figure 4 shows the filter rejection.
0 -20 -40
ATTENUATION - dB
-60 -80 -100 -120
IN+ OUT+
VDD
AD7782
AIN1(+) CS AIN1(-) AIN2(+) AIN2(-) REFIN(+) REFIN(-) GND CONTROLLER
OUT- IN-
-140 -160
DOUT/RDY SCLK XTAL1
0
10
20
30
40
50
60
70
80
90
100
10k
6k
XTAL2
32.768kHz CRYSTAL
FREQUENCY - Hz OUTPUT DATA RATE = 19.8Hz INPUT BANDWIDTH = 4.74Hz 50Hz REJECTION = -66dB, 50Hz 1Hz REJECTION = -60dB 60Hz REJECTION = -117dB, 60Hz 1Hz REJECTION = -94dB
Figure 3. Basic Connection Diagram
Figure 4. Filter Profile (Filter Notches at Both 50 Hz and 60 Hz)
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AD7782
NOISE PERFORMANCE MASTER MODE (MODE = 0)
Table I shows the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for the two input voltage ranges. The numbers are typical and generated at a differential input voltage of 0 V. The peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization noise is added. The device noise is at a low level and is independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source.
Table I. Typical Output RMS Noise and Peak-to-Peak Resolution vs. Input Range
In this mode, SCLK is provided by the AD7782. With CS low, SCLK becomes active when a conversion is complete and generates twenty four falling and rising edges. The DOUT/RDY pin, which is normally high, goes low to indicate that a conversion is complete. Data is output on the DOUT/RDY pin following the SCLK falling edge and is valid on the SCLK rising edge. When the 24-bit word has been output, SCLK idles high until the next conversion is complete. DOUT/RDY returns high and will remain high until another conversion is available. It then operates as a RDY signal again. The part will continue to convert until CS is taken high. SCLK and DOUT/RDY are three-stated when CS is taken high.
SLAVE MODE (MODE = 1)
Input Range 160 mV 2.56 V Noise (V) Peak-to-Peak Resolution (Bits)
DIGITAL INTERFACE
0.65 16.5
2.30 18.5
In slave mode, the SCLK is generated externally. SCLK must idle high between data transfers. With CS low, DOUT/RDY goes low when a conversion is complete. Twenty four SCLK pulses are needed to transfer the digital word from the AD7782. Twenty four consecutive pulses can be generated or, alternatively, the data transfer can be split into batches. This is useful when interfacing to a microcontroller which uses 8-bit transfers. Data is output following the SCLK falling edge and is valid on the SCLK rising edge.
CIRCUIT DESCRIPTION Analog Input Channels
The AD7782's serial interface consists of four signals, CS, SCLK, DOUT/RDY, and MODE. The MODE pin is used to select the master/slave mode of operation. When the part is configured as a master, SCLK is an output while SCLK is an input when slave mode is selected. Data transfers take place with respect to this SCLK signal. The DOUT/RDY line is used for accessing data from the data register. This pin also functions as a RDY line. When a conversion is complete, DOUT/RDY goes low to indicate that data is ready to be read from the AD7782's data register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. The digital conversion is also output on this pin. CS is used to select the device and to place the device in standby mode. When CS is taken low, the AD7782 is powered up, the PLL locks and the device initiates a conversion on the selected channel. The device will continue to convert until CS is taken high. When CS is taken high, the AD7782 is placed in standby mode minimizing the current consumption. The conversion is aborted, DOUT and SCLK are three-stated and the result in the data register is lost. Figure 2 shows the timing diagram for interfacing to the AD7782 with CS used to decode the part.
The ADC has two fully differential input channels. Pin CH1/CH2 is used to select the channels. When CH1/CH2 is low, channel AIN1(+) - AIN1(-) are selected while channel AIN2(+) - AIN2(-) are selected when CH1/CH2 is high. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. The output of the ADC multiplexer feeds into a high-impedance input stage of the buffer amplifier. As a result, the ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). The absolute input voltage range on the ADC inputs is restricted to a range between GND + 100 mV and VDD - 100 mV. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in linearity and noise performance.
Programmable Gain Amplifier
The output from the buffer on the ADC is applied to the input of the on-chip programmable gain amplifier (PGA). The PGA gain range is programmed via pin RANGE. With an external 2.5 V reference applied, the PGA can be programmed to have a bipolar range of 160 mV (RANGE = 0) or 2.56 V (RANGE = 1). These are the ranges that should appear at the input to the on-chip PGA.
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AD7782
Bipolar Configuration/Output Coding
The analog inputs on the AD7782 accept bipolar input voltage ranges. Signals on the AIN(+) input of the ADC are referenced to the voltage on the respective AIN(-) input. For example, if AIN(-) is 2.5 V and the AD7782 is configured for an analog input range of 160 mV, the analog input range on the AIN(+) input is 2.34 V to 2.66 V (i.e., 2.5 V 0.16 V). The coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. The output code for any analog input voltage can be represented as follows:
Code = 2 N -1 x AIN x GAIN / (1.024 x VREF ) + 1
without introducing gain errors in the system. Deriving the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit configuration.
Grounding and Layout
[(
)]
Where AIN is the analog input voltage, GAIN is the PGA gain, i.e., 1 on the 2.56 V range and 16 on the 160 mV range and N = 24.
Crystal Oscillator
The AD7782 is intended for use with a 32.768 kHz watch crystal. A PLL internally locks onto a multiple of this frequency to provide a stable 4.194304 MHz clock for the ADC. The modulator sample rate is the same as the crystal oscillator frequency. The start-up time associated with 32.768 kHz crystals is typically 300 ms. In some cases, it will be necessary to connect capacitors on the crystal to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary depending on the manufacturer's specifications.
Reference Input
Since the analog inputs and reference inputs on the ADC are differential, most of the voltages in the analog modulator are commonmode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided these noise sources do not saturate the analog modulator. As a result, the AD7782 is more immune to noise interference than a conventional high-resolution converter. However, because the resolution of the AD7782 is so high, and the noise levels from the AD7782 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7782 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes as it gives the best shielding. It is recommended that the AD7782's GND pin be tied to the AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. The AD7782's ground plane should be allowed to run under the AD7782 to prevent noise coupling. The power supply lines to the AD7782 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high-resolution ADCs. VDD should be decoupled with 10 F tantalum in parallel with 0.1 F capacitors to GND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 F ceramic capacitors to DGND.
The AD7782 has a fully-differential reference input capability for the channel. The common-mode range for these differential inputs is from GND to VDD. The reference input is unbuffered and therefore excessive R-C source impedances will introduce gain errors. The reference voltage REFIN (REFIN(+) - REFIN(-)) is 2.5 V nominal for specified operation but the AD7782 is functional with reference voltages from 1 V to VDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed as the application is ratiometric. If the AD7782 is used in a nonratiometric application, a low noise reference should be used. Recommended reference voltage sources for the AD7782 include the AD780, REF43, and REF192. It should also be noted that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources like those recommended above (e.g., AD780) will typically have low output impedances and are therefore tolerant to having decoupling capacitors on the REFIN(+)
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AD7782
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink SO Plastic (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-10-
REV. 0
-11-
-12-
C02701-.8-10/01(0)
PRINTED IN U.S.A.

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